1. Field of the Invention
The present invention relates to a semiconductor memory device which comprises a redundancy circuit.
2. Description of the Background Art
FIG. 66 is a circuit diagram showing a configuration of a semiconductor memory device in a first background art. As shown in FIG. 66, the semiconductor memory device of the first background art comprises a normal RAM (Random Access Memory) 101 with 3 bits×32 words and a redundancy RAM 102 with 1 bit×32 words. The redundancy RAM 102 is provided independently from the normal RAM 101, serving as a redundancy circuit of the normal RAM 101.
To the normal RAM 101, a 5-bit address AA<4:0> and a write signal WE are inputted as an address A<4:0> and a write signal WE1, respectively, and further a 3-bit data DI<3:1> is inputted. The normal RAM 101 outputs a 3-bit data DO<3:1>.
To the redundancy RAM 102, a 5-bit address AA<4:0> is inputted as an address A<4:0>, and further a write signal WE2 and a 1-bit data DI<0> are inputted. The redundancy RAM 102 outputs a 1-bit data DO<0>.
The semiconductor memory device of the first background art further comprises selection circuits 103 to 105, 109 and 110, an AND circuit 108 and OR circuits 106 and 107. The selection circuit 103 selects either one of the data DO<3> and the data DO<2> outputted from the normal RAM 101 on the basis of a signal F<3>, and outputs the selected data as data XDO<2> to the outside of the semiconductor memory device. Similarly, the selection circuit 104 selects either one of the data DO<2> and the data DO<1> outputted from the normal RAM 101 on the basis of a signal F<2>, and outputs the selected data as data XDO<1> to the outside of the semiconductor memory device. The selection circuit 105 selects either one of the data DO<1> outputted from the normal RAM 101 and the data DO<0> outputted from the redundancy RAM 102 on the basis of a signal F<1>, and outputs the selected data as data XDO<0> to the outside of the semiconductor memory device.
FIG. 67 is a circuit diagram showing a configuration of the normal RAM 101. As shown in FIG. 67, the normal RAM 101 comprises write drivers WD1a to WD1c, sense amplifiers SA1a to SA1c, a column address decoder 121, a row address decoder 122, column selector circuits 123a to 123c and a plurality of memory cells 120 arranged in a matrix with eight rows and twelve columns. The memory cells 120 in a matrix with eight rows and twelve columns constitute groups of memory cells (memory cell groups) 124a to 124c. In FIGS. 67 and 68 discussed later, the lateral direction of paper is a column direction and the vertical direction is a row direction, and the bit lines and the word lines are arranged in the column direction and the row direction, respectively. Reference numbers 0 to 31 represent respect addresses of the memory cells 120 in the memory cell groups 124a to 124c in a decimal system.
A 2-bit address A<1:0> is inputted to the column address decoder 121 and a 3-bit address A<4:2> is inputted to the row address decoder 122. The row address decoder 122 decodes the address A<4:2> and selects a row which is indicated by the decoded result. The column address decoder 121 decodes the address A<1:0> and notifies the column selector circuits 123a to 123c of the decoded result. Each of the column selector circuits 123a to 123c selects a column indicated by the decoded result which is received. In each of the memory cell groups 124a to 124c, a memory cell 120 indicated by an address A<4:0> is thereby selected.
When the normal RAM 101 outputs data, a signal from the memory cell 120 selected by the memory cell group 124a is amplified by the sense amplifier SA1a and outputted as the data D0<1>. Further, a signal from the memory cell 120 selected by the memory cell group 124b is amplified by the sense amplifier SA1b and outputted as the data DO<2>, and a signal from the memory cell 120 selected by the memory cell group 124c is amplified by the sense amplifier SA1c and outputted as the data DO<3>.
When the write signal WE1=0, i.e., when data is written into the normal RAM 101, the inputted data DI<1> is written into the selected memory cell 120 in the memory cell group 124a through the write driver WD1a. Further, the inputted data DI<2> is written into the selected memory cell 120 in the memory cell group 124b through the write driver WD1b, and the inputted data DI<3> is written into the selected memory cell 120 in the memory cell group 124c through the write driver WD1c. 
FIG. 68 is a circuit diagram showing a configuration of the redundancy RAM 102 serving as the redundancy circuit. As shown in FIG. 68, the redundancy RAM 102 comprises a write driver WD2, a sense amplifier SA2, a column address decoder 131, a row address decoder 132, a column selector circuit 133 and a plurality of memory cells 130 arranged in a matrix with eight rows and four columns. Reference numbers 0 to 31 represent respective addresses of the memory cells 130 in a decimal system. In some cases, the memory cells in the matrix with eight rows and four columns are collectively referred to as “memory cell group 134”.
A 2-bit address A<1:0> is inputted to the column address decoder 131 and a 3-bit address A<4:2> is inputted to the row address decoder 132. The row address decoder 132 decodes the address A<4:2> and selects a row which is indicated by the decoded result. The column address decoder 131 decodes the address A<1:0> and notifies the column selector circuit 133 of the decoded result. The column selector circuit 133 selects a column indicated by the decoded result which is received. In the memory cell group 134, a memory cell 130 indicated by an address A<4:0> is thereby selected.
When the address AA<4:0> has the same value, the address of the memory cell 120 selected in each of the memory cell groups 124a to 124c of the normal RAM 101 is the same as the address of the memory cell 130 selected in the redundancy RAM 102. For example, when a value “01000” in binary is given to the address AA<4:0>, in each of the memory cell groups 124a to 124c of the normal RAM 101, the memory cell 120 having the address 8 in decimal is selected. At this time, also in the redundancy RAM 102, the memory cell 130 having the address 8 in decimal is selected.
When data is outputted from the redundancy RAM 102, a signal from the memory cell 130 selected as above is amplified by the sense amplifier SA2 and outputted as the data DO<0>. When the write signal WE2=0, i.e., when data is written into the redundancy RAM 102, the inputted data DI<0> is written into the selected memory cell 130 through the write driver WD2.
Next, discussion will be made on a data output operation of the semiconductor memory device in the first background art in a case where any one of the memory cell groups 124a to 124c of the normal RAM 101 has a defective memory cell 120. The following discussion will be made on an operation in a case where the memory cell group 124b has a defective memory cell 120, as one example. A signal F<3:0> is a signal outputted from a test circuit (not shown) included in the normal RAM 101, and when the memory cell group 124b has a defect, a signal F<1>=0, a signal F<2>=0 and a signal F<3>=1 are outputted.
Since the signal F<1>=0, the selection circuit 105 outputs the data DO<0> which is outputted from the redundancy RAM 102 as data XDO<0>. Since the signal F<2>=0, the selection circuit 104 outputs the data DO<1> which is outputted from the normal RAM 101 as data XDO<1>. Since the signal F<3>=1, the selection circuit 103 outputs the data DO<3> which is outputted from the normal RAM 101 as data XDO<2>.
Thus, the defective memory cell group 124b in the normal RAM 101 is replaced by the memory cell group 134 in the redundancy RAM 102 which serves as a redundancy circuit, and data from the memory cell 134 in the redundancy RAM 102 is outputted to the outside instead of the data from the memory cell group 124b in the normal RAM 101.
In the above case, the data DO<1> outputted from the normal RAM 101 is outputted to the outside of the semiconductor memory device with its bit position shifted by 1 bit. Specifically, the data DO<1> is outputted from the normal RAM 101 at the least significant bit position and when the data is outputted as the data XDO<1> to the outside of the semiconductor memory device, it is outputted at the second lowest bit position (the data XDO<0> is outputted at the least significant bit position).
When there is no defect in the memory cell groups 124a to 124c, the data DO<3:1> from the normal RAM 101 is outputted to the outside of the semiconductor memory device at the respective bit positions, but since the memory cell group 124b has a defect in the above case, it is necessary to output data to the bit position of the data DO<2> (the second lowest bit position) corresponding to the memory cell group 124b and therefore the data DO<1> is outputted with its bit position shifted by 1 bit. Thus, a replacement method by shifting the bit position of some data is referred to as “I/O shift replacement method”.
Further, a second background art is proposed, as a variation of the semiconductor memory device in the above first background art, in which the redundancy RAM 102 comprises the memory cells 130 as many as one column of memory cells 120 in the normal RAM 101, i.e., 8 memory cells 130, and only one column of memory cells 120 in the normal RAM 101 are replaced by the memory cells 130. In the second background art, if there is a defective memory cell 120 in a column of the memory cell group 124b of the normal RAM 101, for example, when the address A<1:0> indicating the column is inputted to the normal RAM 101, the data DO<0> from the redundancy RAM 102 is outputted to the outside instead of the data DO<2> regardless of the value of the address A<4:2>.
Thus, since the redundancy RAM 102 comprises the memory cells 130 as many as one column of memory cells 120 in the normal RAM 101, it is possible to reduce the circuit scale of the redundancy circuit as compared with the first background art. As to the first and second background arts, the same techniques are disclosed in Japanese Patent Application Laid-Open No. 2001-6391.
Next, the respective problems of the first and second background arts will be discussed.
A. Problem of the First Background Art
In the semiconductor memory device of the first background art, all the memory cells 130 in the redundancy RAM 102 are used when the memory cell group of the normal RAM 101 is replaced by the memory cell group 134 of the redundancy RAM 102. Therefore, when there is a defect in the memory cells 130 of the redundancy RAM 102, the redundancy RAM 102 can not be used as a redundancy circuit. As a result, there arises a problem in the first background art that the manufacturing yield of the semiconductor memory device is not good.
Further, in the first background art, it may be possible to increase the number of bits in the redundancy circuit by providing another redundancy RAM 102 in order to relieve a plurality of memory cell groups which have defects in the normal RAM 101. In this case, as shown in FIG. 69, the first background art using the I/O shift replacement method needs the stages of selection circuits as many as the bits in the redundancy circuit, for outputting data of the normal RAM 101 and the redundancy RAM 102 to the outside of the semiconductor memory device. For this reason, the time required from the data output from the normal RAM 101 or redundancy RAM 102 to the data output to the outside of the semiconductor memory device increases and a desired performance can not be achieved. As a result, there arises a problem that the manufacturing yield of the semiconductor memory device is deteriorated.
Furthermore, in the first background art, since one redundancy RAM 102 can relieve only one normal RAM 101, a plurality of redundancy RAMs 102 are needed to relieve a plurality of normal RAMs 101. Therefore, the circuit scale of the redundancy circuit increases and the percent defective of the redundancy circuit increases. As a result, there arises a problem that the manufacturing yield of the semiconductor memory device is deteriorated.
B. Problem of the Second Background Art
In the semiconductor memory device of the second background art, the memory cells 120 of the normal RAM 101 which are aligned in the column direction, i.e., in the direction that the bit lines extend are replaced by the memory cells 130 of the redundancy RAM 102. In the memory cell groups, defects are caused not only in the column direction but also in the row direction, i.e., in the direction that the word lines extend in some cases. For example of this case, the word line is broken. In such a case, the second background art can not always relieve all the memory cells 120 in the row. Therefore, there arises a problem in the second background art that the manufacturing yield of the semiconductor memory device is not good.